1. Field of the Invention
The present invention relates to a system and method for modelling a hardware component of a data processing apparatus.
2. Background of the Invention
Architects use models to assist making decisions and trade-offs when designing hardware systems. It is common to use different types of models when there are different modelling requirements; common model trade-offs are levels and aspects of accuracy, execution speed, and the cost of developing and using the models.
As an example, a CPU design will often have a netlist representation, providing details of the individual gates and interconnections within the design. Combined with a hardware simulator this provides a model with relatively high level of simulation accuracy whilst being easy to generate.
However, for some applications this model would not be appropriate. For a programmer wanting to simulate software running on the CPU, the simulation speeds will often be too slow, the required tools too expensive, the model format not practical or the netlist IP not available. A common solution for this target audience would be a second “higher level” model such as a Cycle Accurate model which provides a different modelling trade-off, modelling only the aspects required to run the software correctly to the accuracy of a cycle. By reducing the aspects of the design being modelled to only those required by the use scenario, models can be made with reduced complexity, execution time and reliance on particular simulation tools or IP.
In the following description, the term “lower level model” will be used to refer to more detailed larger models, and the term “higher level model” will be used to refer to less detailed smaller models which are typically quicker to run. It will be appreciated that these two terms are relative terms, and hence when comparing two particular models, one will be a higher level model than the other. However, a model that in one situation is viewed as a higher level model may in another situation be viewed as a lower level model, depending on the model with which it is being compared.
Providing an alternative, higher level, model will have an associated cost due to the required development effort. In addition to the development effort, there is often a challenge in under standing how to abstract the aspects captured in one model to another. For example, when modelling a hardware component there are certain observable properties of the hardware component which are more difficult to model, and a good example of this can be demonstrated by considering power consumption.
A number of existing hardware power models have been developed, which have focussed on software and processor power estimation. As an example, the article “Instruction Level Power Analysis and Optimisation of Software”, by V Tiwari et al, Journal of VLSI Signal Processing, 1-18 (1996), introduces the concept of Instruction Level Power Analysis (ILPA) which tries to estimate power of a processor based on the instructions that it executes. In particular, in accordance with this technique, each different type of instruction is annotated with a power value which is then reported every time it executes. This annotation is usually achieved by measuring the power consumed by executing the same instruction multiple times and then averaging the power. The article “Instruction-Level Power Dissipation in the Intel XScale Embedded Microprocessor”, by A Varma et al, University of Maryland, College Park, Md. and Intel Labs, Santa Clara, Calif., extends the ILPA technique to consider other aspects such as interlocks, cache behaviour, etc.
Both of the above described techniques are based on calculating an average value for an observable instruction/condition, and then emitting that average value when the observable instruction or condition is observed again. Such techniques are clearly only useful when modelling processor-type devices where sequences of instructions are being executed. Further, such techniques only provide a relatively approximate indication of power consumed, since they do not take into account the complex interaction between elements of the processor being modelled which may cause variations in power consumption which cannot accurately be modelled merely by associating a particular power consumption with an instruction each time it is observed. Further, such techniques require the presence of identifiable modelled features which already exist, for example a knowledge of what instructions are executed and what power to associate with each type of instruction.
An alternative technique which has been developed for modelling power is known as the “Functional Level Power Analysis” (FLPA) technique, which attempts to model parameters which have an impact on power consumption, and form a relationship between the parameter and the power consumption. For example, the article “Architecture-Level Power Estimation and Design Experiments” by R Chen et al, ACM Transactions on Design Automation of Electronic Systems, Volume 6, Number 1, January 2001, pages 50 to 66, describes a technique which provides cycle-by-cycle power consumption using functional models of processor components. To achieve this, the component to be modelled is analysed, and then power models for the various elements that constitute that component are written (for example based on load model approximations), these individual power models estimating the power consumed by the associated element based on important parameters the designer chooses. This provides a constructed model which can be adjusted to improve accuracy, but requires the writing of explicit models for each of the elements within the component being modelled. In the article, a processor is considered, and a power model written for each of the constituent elements, for example the Arithmetic Logic Unit (ALU), Multiply Accumulate Unit (MAC), Register File, etc. When the operations of these various elements are specified by the instruction stream, the power consumed in each such element is calculated from its power model.
Accordingly, whilst such an approach can provide a higher level of accuracy of power estimation when compared with the earlier-mentioned ILPA technique, such FLPA techniques require a significant amount of modelling effort to produce the various power models for the individual elements of the component, for example the Register File, ALU, MAC, etc, and to generate the input stimulus required to trigger those power models, for example determining when the Register File is used, when the ALU is used, etc.
From the above discussion, it can be seen that a number of techniques are known for estimating values of observable properties of a hardware component that are difficult to model directly, for example power, but these techniques are either relatively inaccurate (e.g. in the ILPA technique as described above) or are relatively complex to implement (for example the FLPA technique as described above).
Another known area of modelling is statistical modelling, and it is known to use such statistical models for design space exploration. Statistical models use knowledge of results from a small sample of inputs to build models capable of predicting results for a much larger set of inputs. When performing hardware design space exploration, there are a huge cross product of options available, which makes detailed simulation very complex and time consuming. As an alternative to such detailed and complex simulation, studies have been performed to seek to use statistical models for such design space exploration, in order to avoid having to run a huge number of simulations in order to get performance metrics (for example cycles per instruction (CPI)) for such a cross product of design parameters (for example pipeline length, cache size, etc). Such statistical modelling techniques are described in the articles “A Predictive Performance Model for Superscalar Processors” by P Joseph et al, the 39th Annual IEEE/ACM International Symposium on Microarchitecture (Micro '06), “Accurate and Efficient Regression Modelling for Microarchitectural Performance and Power Prediction” by B Lee et al, ASPLOS '06, Oct. 21 to 25, 2006, San Jose, Calif., USA, and “Efficiently Exploring Architectural Design Spaces Via Predictive Modelling” by E Ipek et al, ASPLOS '06, Oct. 21 to 25, 2006, San Jose, Calif., USA.
The techniques described in these papers generally take a sample of combinations of design parameters, run on an accurate model, in order to train the parameters of a statistical model. The statistical model is then used to represent all combinations without accurate simulation allowing designers to understand the impact of design parameters. Hence, such techniques are trying to predict a performance metric, such as average CPI, for all combinations of the design space parameters by performing accurate simulation for a few combinations, and then using statistical analysis to interpolate in order to give results for all possible combinations. In addition to inputting design space parameters into the statistical model, in the second paper mentioned above, namely the paper entitled “Accurate and Efficient Regression Modelling for Microarchitectural Performance and Power Prediction”, summary information gathered from an execution run on the accurate model (for example number of cache misses) is also input to the statistical model.
The article “An Empirical Comparison of Algorithmic, Instruction, and Architectural Power Prediction Models for High Performance Embedded DSP Processors” by C Gebotys et al, ISLPED '98, Aug. 10 to 12, 1998, Monterey, Calif. USA, presents a comparison of probabilistic power prediction models at the algorithmic, instruction, and architectural levels for embedded high performance DSP processors. The paper discusses using statistical modelling to verify that an accurate power model can be derived for DSP embedded software. As in the previously mentioned examples, it uses instructions and modelled aspects available from a model to derive its results.
Hence, from the above papers on statistical modelling, it will be appreciated that statistical models can help to significantly reduce complexity, but it is necessary to be able to provide the statistical model with suitable input stimulus in order to enable the statistical model to be able to output reliable values for the modelled aspect. Within the area of design space exploration, statistical models can work well, as there is a lot of information available to base predictions on in order to obtain accurate results. Further, such statistical models have generally been used to produce information of an averaged nature, in particular performance characteristics such as CPI, and have not been used to generate values for observable properties which may vary on a cycle-by-cycle basis. When considering observable properties which are difficult to model, such as power consumption, information available from known power models, for example on a cycle-by-cycle basis, is limited, as only certain aspects are explicitly modelled. As a result, the output from such models will not typically serve as useful input stimulus to a statistical model, and accordingly it has up to now not been possible to readily make use of statistical models when seeking to model such observable properties of a hardware component.
In the unrelated field of computer program testing, it is known to use code coverage techniques to monitor execution patterns of programs. For example, the article “An Approach to Program Testing” by J Huang, Computer Surveys Volume 7, Number 3, September 1975, is an early document providing an introduction to the concept of testing programs by monitoring their execution patterns. This “code coverage” technique is used in program testing to get an idea of the amount of the program behaviour which is exercised by testing. The technique involves annotating code with certain counters and then using these counters to record which statement (statement coverage) or decisions (edge coverage) occur when a program is run. By such techniques, it can be determined what functionality may not have been well tested. The code is often modified by a compiler to add the annotations needed to modify the behaviour.
The article “Code Coverage-Based Power Estimation Techniques for Microprocessors” by G Qu et al, Journal of Circuits, Systems, and Computers, Volume 11, Number 5 (2002), 1-18, describes a code coverage technique for estimating the power consumption of an application running on a processor. This monitors execution of the application program to track which functions/instructions in the application are being executed, and uses this to build up a table of power values associated with functions/instructions during a training phase, and to thereafter determine the power used by an executing application. Accordingly, the technique described therein is in many ways similar to the earlier mentioned ILPA technique, but considers functions instead of just instructions.
It would be useful to develop a technique which would enable observable properties of a hardware component that are not straightforward to model to be modelled by a relatively simple mechanism, thereby avoiding the need to develop complex models which are expensive and take a long time to run.